What Is The Size In Bits Of A Register In The Risc-v Architecture

This article introduces the heady, relatively new RISC-V (pronounced take a chance five) processor architecture and its instruction set up. RISC-5 is a completely open source specification for a reduced instruction set processor. A complete user-mode (non-privileged) instruction ready specification has been released and several inexpensive hardware implementations of this compages are currently available.

Work is ongoing to develop specifications for a number of instruction fix extensions to support general-purpose computing, loftier-performance calculating, and embedded applications that crave minimal code size. Commercially available processors implement many of these developmental extensions.

RISC-V Architecture and Features

The RISC-V compages, publicly announced in 2014, was developed at the University of California at Berkeley by Yunsup Lee, Krste Asanović, David A. Patterson, and Andrew Waterman. This effort followed four previous major RISC architectural design projects at UC Berkeley, leading to the proper noun RISC-V, where V represents the Roman numeral five.

The RISC-5 project began as a make clean sheet with these major goals:

Design a RISC instruction gear up architecture (ISA) suitable for use in a wide variety of applications, spanning the spectrum from micro-power embedded devices to high-performance deject server multiprocessors.
Provide an ISA that is costless to use by anyone for whatever application. This contrasts with the ISAs of almost all other commercially available processors, which are the carefully guarded intellectual property of the company that designed them.
Contain lessons learned from previous decades of processor design, avoiding wrong turns and suboptimal features that other architectures must retain in newer generations to maintain compatibility with previous, sometimes ancient in technological terms, generations.
Provide a small-scale but consummate base ISA suitable for apply in embedded devices. The base of operations ISA is the minimal ready of capabilities any RISC-Five processor must implement. The base of operations RISC-V is a 32-bit processor architecture with 31 general-purpose registers. All instructions are 32 $.25 long. The base ISA supports integer addition and subtraction, merely does not include integer multiplication and partitioning. This is to avert forcing minimal processor implementations to include the fairly expensive multiplication and segmentation hardware for applications that do not require those operations.
Provide optional ISA extensions to support floating-bespeak mathematics, atomic memory operations, and multiplication and segmentation.
Provide additional ISA extensions to support privileged execution modes, like to the x86, x64, and ARM privileged architectures.
Support a compressed teaching set, implementing 16-bit versions of many 32-bit instructions. In processors implementing this extension, 16-fleck instructions may be freely interspersed with 32-flake instructions.
Provide optional ISA extensions to support 64-bit, and even 128-chip, processor word sizes using paged virtual memory on single- and multi-core processors, and in multiprocessing configurations.

RISC-V processors are bachelor today at competitive prices and, given the composure of the ISA design and the advantages of its free-to-employ nature, we tin expect the use of RISC-V processors to abound rapidly in the coming years. RISC-V Linux distributions are available, including all the software development tools needed to build and run applications on RISC-V-based computers and smart devices.

This RISC-5 base ISA register set is presented in the following effigy.

RISC-V base ISA registration RISC-Five base ISA register fix

The registers are 32 bits wide. General-purpose registers x1 through x31 are available for use without any restrictions or special functions assigned past the processor hardware. Register x0 is hardwired to render zero when information technology is read, and will discard any value written to it. We will see some interesting uses of register x0 shortly.

Each register has one or two alternate names as shown in the effigy. These names correspond to the usage of registers in the standard RISC-V application binary interface (ABI). Because registers x1-x31 are functionally interchangeable, it is necessary for the ABI to dictate which register should serve every bit the stack arrow, which registers should contain arguments to functions, which should contain render values, and so forth. The meanings of the register designations are:

ra: Role return address.
sp: Stack pointer.
gp: Global data pointer.
tp: Thread-local data pointer.
t0-t6: Temporary storage.
fp: Frame arrow for function-local stack data (this usage is optional).
s0-s11: Saved registers (if the frame pointer is non in use, x8 becomes s0).
a0-a7: Arguments passed to functions. Whatsoever additional arguments are passed on the stack. Function return values are passed in a0 and a1.

The pc register contains the 32-scrap program counter, holding the accost of the current instruction.

You may be surprised to larn there is no processor flags register in the RISC-V ISA. Some operations that modify flags in other processor architectures instead store their results in a RISC-V register. For case, the signed (slt) and unsigned (sltu) RISC-5 comparison instructions subtract two operands and gear up a destination register to 0 or 1 depending on the sign of the event. A subsequent conditional branch teaching uses the value in that register to make up one's mind which code path to take.

Some of the flags plant in other processors must exist computed in RISC-V. For example, there is no conduct flag. To determine if an addition resulted in a acquit, it is necessary to perform a comparison between the sum and 1 of the operands of the addition instruction. If the sum is greater than or equal to the addend (either addend can be used for the comparison), a carry did not occur; otherwise the addition produced a carry.

Nigh of the base ISA computational instructions use a iii-operand format, in which the first operand is the destination register, the 2d operand is a source register, and the third operand is either a 2nd source register or an immediate value. This is an example three-operand instruction:

add x1, x2, x3

This instruction adds register x2 to x3 and stores the consequence in register x1.

To avoid introducing instructions that are non strictly necessary, many instructions take on extra duties that are performed by defended instructions in other processor architectures. For example, RISC-5 has no didactics that only moves ane annals to some other. Instead, a RISC-5 improver instruction adds a source annals and an immediate value of zero and stores the effect in a destination register, producing the same result. The instruction to transfer register x2 to x1 is therefore add x1, x2, 0, assigning the value (x2 + 0) to x1.

RISC-Five assembly language provides a number of pseudo-instructions using terminology likely to be more familiar to assembly language programmers. The assembler translates the pseudo-instruction mv x1, x2 to a literal add x1, x2, 0. We will discuss pseudo-instructions in more than detail after.

RISC-V Base Instruction Fix

The base RISC-Five instruction ready is equanimous of merely 47 instructions. Viii are system instructions that perform system calls and access performance counters. The remaining 39 instructions fall into the categories of computational instructions, command menses instructions, and retentivity access instructions. We will examine each of these categories in turn.

Computational Instructions

All the computational instructions except lui and auipc use the three-operand form. The first operand is the destination register, the second is a source register, and the third is either a second source annals or an immediate value. Teaching mnemonics using an firsthand value (except for auipc) end with the letter i.

add, addi, sub: Perform improver and subtraction. The immediate value in the addi instruction is a 12-fleck signed value. The sub didactics subtracts the second source operand from the first. At that place is no subi instruction considering addi tin can add together a negative immediate value.
sll, slli, srl, srli, sra, srai: Perform logical left and right shifts (sll and srl), and arithmetics right shifts (sra). Logical shifts insert zero $.25 into vacated locations. Arithmetic right shifts replicate the sign chip into vacated locations. The number of bit positions to shift is taken from the lowest 5 bits of the second source register or from the 5-chip immediate value.
and, andi, or, ori, xor, xori: Perform the indicated bitwise performance on the two source operands. Firsthand operands are 12 bits.
slt, slti, sltu, sltui: The set if less than instructions set up the destination register to one if the first source operand is less than the second source operand: This comparison is in terms of ii'south complement (slt) or unsigned (sltu) operands. Immediate operand values are 12 bits.
lui: Load upper immediate. This education loads bits 12-31 of the destination annals with a xx-bit immediate value. Setting a register to an arbitrary 32-bit immediate value requires two instructions: Beginning, lui sets bits 12-31 to the upper twenty bits of the value. Then addi adds in the lower 12 $.25 to form the complete 32-fleck result. lui has two operands: the destination annals and the immediate value.
auipc: Add upper firsthand to PC. This instruction adds a twenty-scrap immediate value to the upper 20 bits of the program counter. This education enables PC-relative addressing in RISC-V. To form a consummate 32-bit PC-relative accost, auipc forms a partial result, and then an addi education adds in the lower 12 bits.

Control Menstruation Instructions

The provisional branching instructions perform comparisons between ii registers and, based on the result, may transfer control within the range of a signed 12-bit address offset from the current PC. Two unconditional jump instructions are bachelor, one of which (jalr) provides access to the unabridged 32-bit accost range.

beq, bne, blt, bltu, bge, bgeu: Branch if equal (beq), not equal (bne), less than (blt), less than unsigned (bltu), greater or equal (bge), or greater or equal, unsigned (bgeu). These instructions perform the designated comparing betwixt two registers and, if the condition is satisfied, transfer control to the accost commencement provided in the 12-bit signed immediate value.
jal: Jump and link. Transfer command to the PC-relative address provided in the 20-chip signed immediate value and store the address of the next education (the render accost) in the destination annals.
jalr: Jump and link, register. Compute the target address as the sum of the source register and a signed 12- bit immediate value, then jump to that accost and store the accost of the next instruction in the destination register. When preceded by the auipc instruction, the jalr instruction can perform a PC-relative jump anywhere in the 32-scrap address space.

Retention Access Instructions

The retentiveness access instructions transfer information between a register and a memory location. The first operand is the register to exist loaded or stored. The second is a annals containing a memory address. A signed 12-bit immediate value is added to the address in the annals to produce the final address for the load or store.

The load instructions perform sign extension for signed values or zippo extension for unsigned values. The sign or zero extension operation fills in all 32 $.25 in the destination register when a smaller information value (a byte or halfword) is loaded. Unsigned loads are specified by a abaft u in the mnemonic.

lb, lbu, lh, lhu, lw: Load an 8-bit byte (lb), a xvi-fleck halfword (lh) or 32-bit word (lw) into the destination register. For byte and halfword loads, the instruction will either sign-extend (lb and lh) or aught-extend (lbuand lhu) to make full the 32-flake destination register. For instance, the teaching lw x1, sixteen(x2) loads the word at the address (x2 + 16) into register x1.
sb, sh, sw: Store a byte (sb), halfword (sh) or word (sw) to a retentiveness location matching the size of the information value.
fence: Enforce retention access ordering in a multithreaded context. This teaching ensures a coherent view of cached data across threads. contend takes two operands: the first specifies the types of memory accesses that must complete prior to the fence pedagogy. The second specifies the types of memory accesses controlled following the fence. The operation types ordered by this education are retentivity reads and writes (r and w) and I/O device inputs and outputs (i and o). For example, the educational activity debate rw, rw will guarantee that all loads and stores involving retentivity addresses occurring before the argue instruction will complete before any subsequent retentivity loads or stores take place. This instruction ensures that whatever values present in processor caches are properly synchronized with memory or the I/O device.
debate.i: This instruction ensures that any stores to instruction retention have completed before the argue.i instruction completes. This didactics is primarily useful in the context of self-modifying lawmaking.

System Instructions

Of the 8 system instructions, one invokes a system telephone call, ane initiates a debugger breakpoint, and the remaining 6 read and write system command and status registers (CSRs). The CSR manipulation instructions read the current value of the selected CSR into a register, and then update the CSR by either writing a new value, clearing selected bits, or setting selected bits. The source value for the CSR modification is provided in a register or every bit an immediate 5-bit value. CSRs are identified by a 12-bit address. Each CSR instruction performs the read and write of the CSR equally an atomic operation.

ecall: Invoke a arrangement call. Registers used for passing parameters into and returning from the phone call are divers by the ABI, not by processor hardware.
break: Initiate a debugger breakpoint.
csrrw, csrrwi, csrrc, csrrci, csrrs, csrrsi: Read the specified CSR into a destination register and either write a source operand value to the register (csrrw), articulate whatsoever 1 fleck in the source operand in the annals (csrrc), or set whatever ane chip in the source operand in the annals (csrrs). These instructions take three operands: The get-go is the destination annals receiving the value read from the CSR, the second is the CSR address, and the third is a source annals or a 5-flake immediate value (i suffix).

Six CSRs are defined in the base of operations RISC-V architecture, all read-just. To execute any of the CSR access instructions in a read-only way, register x0 must be provided as the 3rd operand. These registers define three 64-flake functioning counters:

cycle, cycleh: The lower (cycle) and upper (cycleh) 32 bits of the 64-bit count of elapsed arrangement clock cycles since a reference time, typically system startup. The frequency of the organisation clock may vary if dynamic voltage and frequency scaling (DVFS) is active.
time, timeh: These are the lower (time) and upper (timeh) 32 bits of the 64-bit count of elapsed real-time clock cycles since a reference fourth dimension, typically system startup.
instret, instreth: The lower (instret) and upper (instreth) 32 bits of the 64-bit count of processor instructions retired.

The two 32-bit halves of each functioning counter cannot be read in a single atomic operation. To preclude erroneous readings, the post-obit procedure should exist used to reliably read each of the 64-bit counters:

Read the upper 32 $.25 of the counter into a register.
Read the lower 32 $.25 of the counter into another register.
Read the upper 32 bits into however another register.
Compare the first and second reads of the upper 32 counter $.25. If they differ, jump back to footstep one.

This procedure will read a valid count value even though the counter continues to run between the reads. In general, execution of this sequence should require at nigh one backward jump in footstep four.

Pseudo-Instructions

The RISC-V architecture has a truly reduced instruction set, lacking several types of instructions present in the instruction sets of other processor architectures. The functions of many of those more than familiar instructions can be performed with RISC-Five instructions, though perchance not in an immediately intuitive mode.

The RISC-V assembler supports a number of pseudo-instructions, each of which translates to one or more than RISC-5 instructions providing a type of functionality one might look in a general-purpose processor didactics set. The post-obit tabular array presents a few of the most useful RISC-V pseudo-instructions:

Pseudo-instruction	RISC-Five educational activity(due south)	Function
`nop`	`addi x0, x0, 0`	No operation
`mv rd,rs`	`addi rd, rs, 0`	Copy `rs` to `rd`
`not rd, rs`	`ori rd, rs, -ane`	`rd` = `Not rs`
`neg rd, rs`	`sub rd, x0, rs`	`rd` = `-rs`
`j get-go`	`jal x0, offset`	Unconditional jump
`jal offset`	`jal x1, offset`	Nigh function call (xx-flake outset)
`call offset`	`auipc x1, offset[31:12] + offset[xi]` `jalr x1, starting time[11:0](x1)`	Far function telephone call (32-bit offset)
`ret`	`jalr x0, 0(x1)`	Return from function
`beqz rs, beginning`	`beq rs, x0, showtime`	Branch if equal to zero
`bgez rs, offset`	`bge rx, x0, offset`	Branch if greater than or equal to aught
`bltz rs, offset`	`blt rs, x0, offset`	Branch if less than naught
`bgt rs, rt, offset`	`blt rt, rs, offset`	Branch if greater than
`ble rs, rt, offset`	`bge rt, rs, outset`	Branch if less than or equal
`fence`	`debate iorw, iorw`	Fence all memory and I/O accesses
`csrr rd, csr`	`csrrw rd, csr, x0`	Read a CSR
`li rd, immed`	`addi rd, x0, immed`	Load 12-bit firsthand
`li rd, immed`	`lui rd, immed[31:12] + immed[11]` `addi rd, x0, immed[11:0]`	Load 32-chip immediate
`la rd, symbol`	`auipc rd, delta[31:12] + delta[eleven]` `addi rd, rd, delta[11:0]`	Load the address of symbol, where `delta` = `(symbol-pc)`
`lw rd, symbol`	`auipc rd, delta[31:12] + delta[xi]` `lw rd, rd, delta[xi:0](rd)`	Load give-and-take at symbol, where `delta` = `(symbol-pc)`
`sw rd, symbol, rt`	`auipc rt, delta[31:12] + delta[11]` `sw rd, rd, delta[11:0](rt)`	Store word at symbol, where `delta` = `(symbol-pc)`

RISC-V pseudo-instructions

In these instruction listings, rd is the destination register, rs is the source register, csr is a command and status register, symbol is an absolute information address, and commencement is a PC-relative instruction address.

Instructions combining the upper 20 $.25 of an address or immediate value with an immediate value containing the lower 12 bits must perform a step to opposite the outcome of the sign extension of chip eleven of the lower 12-bit value in the 2nd instruction of each sequence. This is necessary because the immediate value in the addi educational activity is ever treated every bit signed. The near significant flake of the 12 scrap immediate value will be sign-extended through scrap 31 earlier beingness added to the upper twenty bits.

The following instance demonstrates the trouble and the solution. Presume we want to load the value 0xFFFFFFFF into a register using lui and addi and naively add the upper and lower portions:

The addi instruction sign-extends 0xFFF to 0xFFFFFFFF before adding it to 0xFFFFF000. The result of the addition is and so 0xFFFFEFFF, which is not what we want. Calculation bit 11 of the lower 12 bits to the upper 20 bits will fix this:

The consequence is now 0xFFFFFFFF, the correct value. This process will work for whatsoever other numeric value. If fleck 11 happens to be zero, nothing will be added to the upper 20 bits.

Privilege Levels

The RISC-V architecture defines 3 privilege levels at which a thread can run:

User (U) privilege level
Supervisor (Southward) privilege level
Automobile (M) privilege level

All RISC-V implementations must back up Yard mode, the most privileged level, capable of accessing all organisation features. M fashion is entered at organisation reset. The code in a simple embedded organization might run entirely in Grand fashion.

In a slightly more than sophisticated use instance, a secure boot process might run at the One thousand privilege level, loading and starting an application that runs in U style. This approach is advisable for a secure embedded solution.

In addition to the mandatory M level, A RISC-Five processor may implement either or both of the Due south and U privilege levels. A system running a general-purpose operating system uses Southward fashion and U way in the same mode every bit the kernel and user modes of other common processor architectures. RISC-V U mode applications request system services with the ecall (environment telephone call) instruction, generating an exception handled at the S level. The privilege compages of RISC-V directly supports mod operating systems such as Linux.

Split up collections of CSRs are divers to enable configuration, control, and monitoring of the system at each of the three privilege levels. Depending on the privilege level of the running thread and the level of a CSR, the thread may take read-write, read-only, or no access to the CSR. Threads at higher privilege levels can access CSRs at lower privilege levels.

The RISC-V Southward privilege level supports paged virtual retentiveness with a 32-flake address space divided into 4KB pages. A 32-chip virtual accost is separated into a 20-bit virtual page number and a 12-bit page offset. 2 additional virtual memory configurations are defined for the RISC-V 64-bit environs. One is a 39-bit address space, supporting 512GB of virtual memory. For applications requiring even more virtual addresses, a 48-bit address space is available, supporting 256TB of virtual retentiveness. Although the 48-bit configuration offers far more memory than the 39-scrap version, it also requires additional storage for page tables and consumes more processing fourth dimension during traversal of those tables.

The post-obit instructions support privileged execution levels:

mret, sret, uret – These instructions return from the exception handler initiated past an ecall instruction. Each of these instructions can be executed at the privilege level indicated by the start letter of the pedagogy or higher. Executing i of these instructions referencing a privilege level lower than that of the current thread volition return from the exception initiated at the lower level.
wfi – Wait for interrupt. This instruction requests the current thread to stall until an interrupt becomes available for servicing. The RISC-V specification only requires that this education serve as a hint, so a detail implementation may process a wfi instruction as a no-op rather than really stalling the thread. Considering it is possible for the processor to handle wfi as a no-op, code that follows a wfi instruction must explicitly check for the presence of awaiting interrupts in demand of processing. This sequence typically occurs inside a loop.
sfence.vma – Flush virtual retentivity page table data from cache to retentivity. The leading south in the instruction mnemonic indicates this instruction is targeted for use at the supervisor privilege level.

Nosotros won't cover the topic here, but RISC-V also defines instructions and CSRs supporting virtualization and the hypervisor that manages the virtual environment.

RISC-V Extensions

The instruction set described in this section is named RV32I, which stands for the RISC-V 32-bit integer instruction set. Although the RV32I ISA provides a complete and useful educational activity set up for many purposes, it lacks several functions and features bachelor in other processors such as x86 and ARM.

The RISC-V extensions provide a mechanism for calculation capabilities to the base instruction prepare in an incremental and compatible style. Implementors of RISC-5 processors can selectively include extensions in a processor blueprint to optimize tradeoffs between fleck size, organisation capability, and operation.

G Extension

The RISC-V M extension adds integer multiplication and partitioning functionality to the base RV32I instruction fix. The following instructions are available in this extension:

mul: Multiply two 32-scrap registers and store the lower 32 bits of the result in the destination annals.
mulh. mulhu, mulhsu: Multiply 2 32-bit registers and store the upper 32 bits of the result in the destination register. Treat the multiplicands as both signed (mulh), both unsigned (mulhu), or signed rs1 times unsigned rs2 (mulhsu). rs1 is the outset source annals in the instruction and rs2 is the second.
div, divu : Perform partitioning of ii 32-bit registers, rounding the event toward zero, on signed (div) or unsigned (divu) operands.
rem, remu: Return the residuum corresponding to the upshot of a div or divu pedagogy on the operands.

Division by aught does not enhance an exception. To discover segmentation by zero, code should test the divisor and branch to an appropriate handler if information technology is goose egg.

A Extension

The RISC-V A extension provides atomic read-alter-write operations to support multithreaded processing in shared memory.

The diminutive load-reserved (lr.due west) and store-conditional (sc.w) instructions work together to perform a memory read followed past a write to the aforementioned location equally an atomic sequence. The load-reserved education places a reservation on the retentivity address during the load. If some other thread writes to the same location while the reservation is in effect, the reservation is cancelled.

When the store-conditional educational activity executes, it returns a value indicating if it successfully completed the atomic operation. If the reservation remains valid (in other words, no intervening write occurred to the target accost), the store-provisional instruction writes the register to memory and returns zero, indicating success. If the reservation was cancelled, the store-conditional instruction does not alter the retentivity location and returns a non-null value indicating the store operation failed. The following instructions implement the load-reserved and store-provisional operations:

lr.westward: Load a register from a memory location and place a reservation on the address.
sc.w: Store a register to a memory location conditionally. Fix the destination annals to nil if the operation succeeded and the retentiveness location was written, or set the destination annals to a nonzero value if the reservation was cancelled. If the reservation was cancelled, the retentiveness location is not modified past this instruction.

The atomic retentiveness operation (AMO) instructions atomically load a word from a retentivity location into the destination annals, perform a binary operation betwixt the value read and rs2, and store the result dorsum to the retention address. The post-obit instructions implement the AMO operations:

amoswap.w: Atomically swap rs2 into the rs1 retentivity location.
amoadd.west: Atomically add rs2 into the rs1 memory location.
amoand.w,amoor.w,amoxor.w: Atomically perform AND, OR, or XOR with rs2 into the rs1 retentivity location.
amomin.w,amominu.due west,amomax.due west,amomaxu.westward: Atomically perform minimum or maximum selection of signed or unsigned (instructions with the u suffix) values with rs2 into the rs1 memory location.

C Extension

The RISC-V C extension implements compressed instructions with the goals of minimizing the amount of retentivity consumed by instruction storage and reducing the amount of charabanc traffic required to fetch instructions.

All RV32I instructions discussed previously are 32 bits in length. The C extension provides alternate 16-fleck representations of many of the near ofttimes used RV32I instructions. Each compressed instruction is equivalent to one full-length instruction. No mode switching is necessary, meaning programs can freely intermix 32-chip RV32I instructions and compressed xvi-bit instructions. In fact, assembly linguistic communication programmers practise not even demand to take steps to specify whether an didactics should be generated in compressed form. The assembler and linker are capable of transparently emitting compressed instructions where possible to minimize code size with no execution functioning punishment.

When working with processors and software evolution tool sets supporting the RISC-Five C extension, the benefits of compressed instructions are immediately available to developers working in associates language likewise as to those working with college-level languages.

F and D Extensions

The RISC-V F and D extensions provide hardware back up for single-precision (F) and double-precision (D) floating-point arithmetics in accordance with IEEE 754. The F extension adds 32 floating-betoken registers named f0-f31 and a command and condition annals named fcsr to the compages. These registers are all 32 bits. The extension includes a set of floating-point instructions that complies with the requirements in the IEEE 754-2008 unmarried-precision standard.

Near floating-point instructions operate on the floating-point registers. Data transfer instructions are provided to load floating-betoken registers from retention, store floating-point registers to retention, and move data betwixt floating-bespeak registers and integer registers.

The D extension widens f0-f31 to 64 bits. In this configuration, each f register can concur a 32-bit value or a 64-bit value. Double-precision floating-betoken instructions are added, in compliance with the IEEE 754-2008 double-precision standard. The D extension requires the F extension be present.

More Extensions

Several additional extensions to the RISC-V architecture have been defined, are in evolution, or are at to the lowest degree under consideration for future evolution:

RV32E architecture : This is non really an extension, rather it is a modified architecture intended to reduce processor hardware requirements below those of the RV32I instruction ready for small embedded systems. The but difference between RV32I and RV32E is the reduction in the number of integer registers to 15. This change is expected to reduce processor dice area size and power consumption by about 25% compared to an otherwise equivalent RV23I processor. x0 remains a dedicated zero register. Halving the number of registers frees up one fleck in each register specifier in an instruction. These $.25 are guaranteed to remain unused in hereafter revisions and are thus available for utilize in customized instruction extensions.
Q extension: The Q extension supports 128-bit quad-precision floating-point mathematics as defined in IEEE 754-2008.
L extension: The 50 extension supports decimal floating-betoken arithmetic as divers in IEEE 754-2008.
B extension: The B extension supports chip manipulations such as inserting, extracting, and testing individual $.25.
J extension: The J extension supports dynamically translated languages such every bit Java and JavaScript.
T extension: The T extension supports memory transactions consisting of diminutive operations beyond multiple addresses.
P extension: The P extension provides packed SIMD instructions for floating-point operations in pocket-sized RISC-V systems.
Five extension: The V extension supports information-parallel, or vector, operations. The Five extension does not specify the lengths of data vectors; that determination is left to the implementers of a RISC-V processor design. A typical implementation of the V extension might support 512-bit data vectors, though implementations with up to 4,096-bit vector lengths are currently available.
Due north extension: The Northward extension provides support for treatment interrupts and exceptions at the U privilege level.
Zicsr extension: The Zicsr extension performs atomic read-change-write operations on the system CSRs. These instructions are described in the Arrangement instructions department.
Zifencei extension: The Zifencei extension defines the fence.i pedagogy, described in the Memory admission instructions section.

The next section covers the extension of the base RISC-5 ISA to 64 bits.

64-bit RISC-V

The RISC-V introduction to this point has discussed the 32-flake RV32I architecture and education set, with extensions. The RV64I educational activity fix extends RV32I to a 64-bit architecture. As in RV32I, instructions are 32-bits wide. In fact, the RV64I instruction set is most entirely the same as RV32I except for a few significant differences:

All of the integer registers are widened to 64 bits.
Addresses are widened to 64 $.25.
Chip shift counts in education opcodes increase in size from 5 to half dozen bits.
Several new instructions are defined to operate on 32-bit values in a style equivalent to RV32I. These instructions are necessary because most instructions in RV64I operate on 64-bit values and at that place are many situations in which information technology is necessary to operate efficiently on 32-bit values. These word-oriented instructions take an opcode mnemonic suffix of due west. The w-suffix instructions produce signed 32-bit results. These 32-bit values are sign-extended (even if they are unsigned values) to fill the 64-bit destination annals. In other words, bit 31 of each result is copied into bits 32-63.

The following new instructions are divers in RV64I:

addw, addiw, subw, sllw, slliw, srlw, srliw, sraw, sraiw: These instructions perform equivalently to the RV32I instruction with the aforementioned mnemonic, minus the w suffix. They work with 32-bit operands and produce 32-bit results. The result is sign-extended to 64 bits.
ld, sd: Load and store a 64-bit doubleword. These are the 64-fleck versions of the lw and sw instructions in the RV32I instruction set up.

The remaining RV32I instructions perform the aforementioned functions in RV64I, except addresses and registers are 64 bits in length. The same opcodes, both in assembly source lawmaking and binary auto code, are used in both instruction sets.

In the next section, we will examine some standard 32-bit and 64-bit RISC-V configurations that are commercially available. Each of these consists of a base of operations ISA plus selected extensions.

Standard RISC-5 Configurations

The RV32I and RV64I educational activity sets provide a base fix of capabilities useful mainly in smaller embedded organisation designs. Systems intended to support multithreading, multiple privilege levels, and general-purpose operating systems require several of the RISC-V extensions to operate correctly and efficiently.

The minimum RISC-V configuration recommended for establishing an application development target consists of a base of operations RV32I or RV64I didactics fix architecture augmented with the I, One thousand, A, F, D, Zicsr, and Zifencei extensions. The abbreviation for this combination of features is G, as in RV32G or RV64G. Many 1000 configurations additionally support the compressed instruction extension, with the names RV32GC and RV64GC.

In embedded applications, a mutual configuration is RV32IMAC, providing the base of operations educational activity set plus multiply/split functionality, diminutive operations, and compressed instruction back up. Marketing materials for RISC-V processors frequently apply these shorthand descriptions of processor capabilities.

The post-obit section presents a small example of RISC-V associates linguistic communication.

RISC-5 Assembly Language

This RISC-V assembly linguistic communication example is a consummate application that runs on a RISC-V processor:

This program prints the following text in a panel window and so exits.

Howdy, Computer Builder!

These are some points of involvement within the associates code:

The %pcrel_hi and %pcrel_lo directives select the high 20 bits (%pcrel_hi) or low 12 bits (%pcrel_lo) of the PC-relative address of the characterization provided as an argument. The combination of the auipc and addi instructions places the address of the message cord in a0.
1: is a local label. When referencing a local label, the letter b is appended to reference a label before in the code (backwards), or f is appended to reference a label afterward in the code (forward). The %pcrel_hi and %pcrel_lo directives are paired: The 1: local label resolves the lower 12 bits of the offset to the msg: accost.

Summary

This article introduced the RISC-Five processor architecture and its pedagogy set up. The RISC-Five project has divers a complete user-mode educational activity set specification and a number of extensions to support general-purpose calculating, high-functioning computing, and embedded applications requiring minimal code size. RISC-V processors are offered commercially, and open source products are available to implement instantiations of RISC-Five in FPGA devices.

This article is adapted from my new book, Modern Computer Compages and Organization, published past Packt Publishing. The book includes chapter exercises that become you started with RISC-V development using freely available tools. These exercises, forth with case solutions, are bachelor at the book GitHub repository.

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